Special function registers
An area of data memory is dedicated to registers that are required for configuration and dataflow control. This dedicated memory area is divided into a number of special function registers which can not be used as general purpose registers by the programmer. The special function registers are TMR0, OPTION, PCL, STATUS, FSR, PORTA, PORTB, TRISA, TRISB, EEDATA, EECON1, EEADR, EECON2, PCLATH and INTCON and are situated in the data memory locations shown in Figure below
File Address
Register Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit2
Bit 1
Bit 0
Value on
Power-On
Reset
Value on
Other
Resets
Bank 0 0x00 INDF Uses contents of FSR to address data memory (not a physical register) ---- ---- ---- ---- 0x01 TMR0 8-bit real-time clock/counter xxxx xxxx uuuu uuuu 0x02 PCL Least Significant 8 bits of the Program Counter (PC) 0000 0000 0000 0000 b7 b6 b5 b4 b3 b2 b1 b0 0x03 STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu 0x04 FSR Indirect data memory address pointer 0 xxxx xxxx uuuu uuuu 0x05 PORTA - - - RA4/
T0CKI
RA3 RA2 RA1 RA0 ---x xxxx ---u uuuu 0x06 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 0x07 Unimplemented Unimplemented location, read as '0 ---- ---- ---- ---- 0x08 EEDATA EEPROM data register xxxx xxxx uuuu uuuu 0x09 EEADR EEPROM address register xxxx xxxx uuuu uuuu 0x0A PCLATH - - - Most Significant 5 Bits of the PC ---0 0000 ---0 0000 b12 b11 b10 b9 b8 0x0B INTCON GIE EEIE T0IE INT E RBIE T0IF INTF RBIF 0000 000x 0000 000u Bank 1 0x80 INDF Uses contents of FSR to address data memory (not a physical register) ---- ---- ---- ---- 0x81 OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 0x82 PCL Least Significant 8 bits of the Program Counter (PC) 0000 0000 0000 0000 0x83 STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu 0x84 FSR Indirect data memory address pointer 0 xxxx xxxx uuuu uuuu 0x85 TRISA - - - PORTA data direction register ---1 1111 ---1 1111 b4 b3 b2 b1 b0 0x86 TRISB PORTB data direction register 1111 1111 1111 1111 b7 b6 b5 b4 b3 b2 b1 b0 0x87 Unimplemented Unimplemented location, read as '0 ---- ---- ---- ---- 0x88 EECON1 - - - EEIF WRERR WREN WR RD ---0 x000 ---0 q000 0x89 EECON2 EEPROM control register 2 (not a physical register) ---- ---- ---- ---- 0x8A PCLATH - - - Most Significant 5 Bits of the PC ---0 0000 ---0 0000 b12 b11 b10 b9 b8 0x8b INTCON GIE EEIE T0IE INT E RBIE T0IF INTF RBIF 0000 000x 0000 000u Legend: x = unknown, u = unchanged. - = unimplemented read as ’0’, q = value depends on condition. Special Function Registers (SFR)
0x stands for hexadecimal
The Status Register
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
IRP RP1 RP0 TO PD Z DC C
The STATUS register is of most importance to programming the PIC, it contains the arithmetic status of the ALU (Arithmetic Logic Unit), the RESET status and the bank select bit for data memory. As with any register, the STATUS register can be the destination for any instruction. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged).
The first three bits (STATUS<0> to STATUS<2>) are the carry (C), digit carry (DC) and zero (Z) flags of the ALU respectively. The values of these bits change depending on the results of arithmetic or logical operations performed during program execution. Bits 3 and 4 are the power down PD and watchdog timer timeout TO bits respectively and bits 5and6(RP0 and RP1) are the bank selection bits.
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD Z DC C
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R = Readable bit
W= Writable bit
U = Unimplemented bit, read as ‘0’
-n= Value at POR reset
bit 7:
IRP: Register Bank Select bit (used for indirect addressing)
0 = Bank 0, 1 (00h - FFh)
1 = Bank 2, 3 (100h - 1FFh)
The IRP bit is not used by the PIC16F8X. IRP should be maintained clear.
bit 6-5:
RP1:RP0: Register Bank Select bits (used for direct addressing)
00 = Bank 0 (00h - 7Fh)
01 = Bank 1 (80h - FFh)
10 = Bank 2 (100h - 17Fh)
11 = Bank 3 (180h - 1FFh)
Each bank is 128 bytes. Only bit RP0 is used by the PIC16F8X. RP1 should be maintained clear.
bit 4:
TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3:
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2:
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit (for ADDWF and ADDLW instructions) (For borrow the polarity is reversed)
bit 1:
DC: Digit carry/borrow
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit (for ADDWF and ADDLW instructions)
bit 0:
C: Carry/borrow
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note: For borrow the second operand the polarity is reversed. A subtraction is executed by adding the two’s complement of. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.
The INTCON Register
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
GIE EEIE T0IE INTE RBIE T0IF INTF RBIF
The INTCON register is a readable and writable register which contains the various enable bits for all interrupt sources.
The meaning of INTCON might be (though this is only me thinking) INTurrpt CONtrol register. I have serached the net for the source of this acronym with no avail; if you find it please e-mail me.
Anyway, interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>).
This register is used to configure the interrupt control logic circuitry. Bits 0 to 6 are used to configure the interrupt enable/disable statuses and the interrupt flags for the four interrupt sources. No interrupt to the CPU will result unless the GIE bit is set. The GIE bit is the bit INTCON<7> and when set, enables all un-masked interrupts.
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE EEIE T0IE INTE RBIE T0IF INTF RBIF
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R = Readable bit
W= Writable bit
U = Unimplemented bit, read as ‘0’
-n= Value at POR reset
bit 7:
GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interruptsbit 6
EEIE: EE Write Complete Interrupt Enable bit
1 = Enables the EE write complete interrupt
0 = Disables the EE write complete interrupt
bit 5
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4:
INTE: RB0/INT Interrupt Enable bit
1 = Enables the RB0/INT interrupt
0 = Disables the RB0/INT interrupt
bit 3:
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2:
T0IF: TMR0 overflow interrupt flag bit
1 = TMR0 has overflowed (must be cleared in software)
0 = TMR0 did not overflow
bit 1:
INTF: RB0/INT Interrupt Flag bit
1 = The RB0/INT interrupt occurred
0 = The RB0/INT interrupt did not occur
BIT 0:
RBIF: RB Port Change Interrupt Flag bit
1 = When at least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
The Option Register
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
The OPTION register in the PIC 16f84 microcontroller is a readable and writable register which contains various control bits to configure the TMR0/WDT prescaler, the external INT interrupt, TMR0, and the weak pull-ups on PORTB.
Bits 0, 1 and 2 are the three prescaler division ratio bits for either the timer/counter module or the watchdog timer WDT, depending on which of these have been allocated for use.
Bit 3 selects the assignment of the prescaler/postscaler to either the timer/counter, or the watchdog timer.
Bit 4 selects whether the timer/counter increments on the falling edge or the rising edge of the external square wave signal on pin TOCKI when external timer clocking is selected; otherwise, the waveform is ignored.
Bit 5 is used to choose between external timer clocking via the TOCKI pin, or via the internal instruction cycle clock.
Bit 6 selects between interrupt triggering on either a rising or falling edge.
Bit 7 enables or disables the weak internal pull-ups on the pins of PORTB when the port is configured as an input. The pull-ups are disabled when the port is in output mode.
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R = Readable bit
W= Writable bit
U = Unimplemented bit, read as ‘0’
-n= Value at POR reset
bit 7:
RBPU: PORTB Pull-up Enable bit
0 = PORTB pull-ups are disabled
1 = PORTB pull-ups are enabled (by individual port latch values).
bit 6
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5
T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4:
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3:
PSA: Prescaler Assignment bit
1 = Prescaler assigned to the WDT
0 = Prescaler assigned to TMR0bit 2,1,0:
PS2:PS0: Prescaler Rate Select bits
Bit Value TMR0 Rate WDT Rate 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128